50 lines
1.4 KiB
Diff
50 lines
1.4 KiB
Diff
From c43196265f6a993367b7f277cf0cdd091574bc8b Mon Sep 17 00:00:00 2001
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From: Sean Cross <xobs@kosagi.com>
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Date: Mon, 27 Apr 2015 10:40:13 +0800
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Subject: [PATCH 25/65] ASoC: es8328: Set clock rates when setting DAI format
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The clock rate should be set when the I2C devices is instantiated.
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However, there is a divide-by-two that gets stuck somewhere, which
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resets the clock rate.
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Set the clock rates again prior to setting everything up to get
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around this problem.
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Signed-off-by: Sean Cross <xobs@kosagi.com>
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(sakaki: upstream has changed a lot, clock reset code simplified)
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---
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diff a/sound/soc/codecs/es8328.c b/sound/soc/codecs/es8328.c
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--- a/sound/soc/codecs/es8328.c
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+++ b/sound/soc/codecs/es8328.c
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@@ -477,6 +477,9 @@
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return 0;
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}
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+static int es8328_set_sysclk(struct snd_soc_dai *codec_dai,
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+ int clk_id, unsigned int freq, int dir);
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+
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static int es8328_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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@@ -487,10 +490,15 @@
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int reg;
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int wl;
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int ratio;
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+ int clk_rate;
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if (!es8328->sysclk_constraints) {
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- dev_err(codec->dev, "No MCLK configured\n");
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- return -EINVAL;
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+ clk_rate = clk_get_rate(es8328->clk);
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+ es8328_set_sysclk(dai, ES8328_MCLK, clk_rate, 0);
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+ if (!es8328->sysclk_constraints) {
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+ dev_err(codec->dev, "No MCLK configured\n");
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+ return -EINVAL;
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+ }
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}
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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--
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2.7.3
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