mirror of https://git.freebsd.org/ports.git
77 lines
2.8 KiB
Makefile
77 lines
2.8 KiB
Makefile
PORTNAME= surelog
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DISTVERSIONPREFIX= v
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DISTVERSION= 1.82
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CATEGORIES= cad
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MAINTAINER= yuri@FreeBSD.org
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COMMENT= SystemVerilog 2017 Pre-processor, Parser, Elaborator, etc
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WWW= https://github.com/chipsalliance/Surelog
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LICENSE= APACHE20
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LICENSE_FILE= ${WRKSRC}/LICENSE
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BROKEN_aarch64= compilation fails: Creating OVM precompiled package... Segmentation fault (core dumped) # update to the current revision might help but it has C++ errors
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BROKEN_armv6= compilation fails: Creating OVM precompiled package... libunwind: personality function returned unknown result 5
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BROKEN_i386= compilation fails: conversion function cannot be redeclared, see https://github.com/chipsalliance/Surelog/issues/3206
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BUILD_DEPENDS= utf8cpp>0:devel/utf8cpp \
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${PYTHON_PKGNAMEPREFIX}orderedmultidict>0:devel/py-orderedmultidict@${PY_FLAVOR}
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BUILD_DEPENDS+= googletest>0:devel/googletest # workaround for https://github.com/chipsalliance/Surelog/issues/3826
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LIB_DEPENDS= libcapnp.so:devel/capnproto \
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libuhdm.so:cad/uhdm
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TEST_DEPENDS= googletest>0:devel/googletest
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USES= cmake:testing compiler:c++17-lang localbase:ldflags tcl:86,build
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USE_JAVA= 17 # Java selection fails in cmake when Java 11 is also installed, see https://gitlab.kitware.com/cmake/cmake/-/issues/24674
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USE_LDCONFIG= ${PREFIX}/lib ${PREFIX}/lib/surelog
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JAVA_BUILD= yes
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JAVA_RUN= no
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USE_GITHUB= yes
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GH_ACCOUNT= chipsalliance
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GH_PROJECT= Surelog
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GH_TUPLE= alainmarcel:antlr4:a27cf84:antlr4/third_party/antlr4 \
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nlohmann:json:788e546:json/third_party/json
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CMAKE_ON= BUILD_SHARED_LIBS \
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SURELOG_USE_HOST_UHDM \
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SURELOG_USE_HOST_CAPNP \
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SURELOG_USE_HOST_GTEST
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CMAKE_OFF= SURELOG_BUILD_TESTS
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CMAKE_ARGS= -DFREEBSD_JAVA_VERSION=${USE_JAVA} \
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-DPython3_EXECUTABLE=${PYTHON_CMD}
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CMAKE_TESTING_ON= SURELOG_BUILD_TESTS # 2 tests fail, see https://github.com/chipsalliance/Surelog/issues/3545
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CMAKE_TESTING_TARGET= UnitTests
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BINARY_ALIAS= python3=${PYTHON_CMD} tclsh=${TCLSH}
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CONFLICTS_BUILD= openjdk8 openjdk11 openjdk18 openjdk19
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OPTIONS_DEFINE= PYTHON TCMALLOC
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OPTIONS_DEFAULT= PYTHON TCMALLOC # should be the same TCMALLOC default as in cad/yosys, cad/uhdm because surelog's lib is used in the yosys plugin cad/yosys-systemverilog
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OPTIONS_SUB= yes
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PYTHON_USES= python
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PYTHON_USES_OFF= python:build
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PYTHON_BUILD_DEPENDS= swig:devel/swig
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PYTHON_CMAKE_BOOL= SURELOG_WITH_PYTHON
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PYTHON_CMAKE_ON= -DFREEBSD_PYTHON_DISTVERSION=${PYTHON_DISTVERSION}
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TCMALLOC_CMAKE_BOOL= SURELOG_WITH_TCMALLOC
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TCMALLOC_LIB_DEPENDS= libtcmalloc.so:devel/google-perftools
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PORTSCOUT= limit:^.*[0-9]\.[0-9] # prevent tags like 'show'
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post-install:
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# workaround for https://github.com/chipsalliance/Surelog/issues/3965
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# - surelog fails to create package files on some systems, and succeeds on others
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# - so we remove this directory altogether for now
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@${RM} -r \
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${STAGEDIR}${DATADIR}
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post-test:
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cd ${BUILD_WRKSRC} && ctest
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.include <bsd.port.mk>
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